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[VHDL-FPGA-Verilog] ima_adpcm_encoder_latest.tar

Description: This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1. PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.
Platform: | Size: 23552 | Author: Arun | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[VHDL-FPGA-Verilog] UARTtransmitter

Description: UART Transmitter. VHDL code and its testbench.
Platform: | Size: 2048 | Author: mehmet | Hits:

[VHDL-FPGA-Verilog] register

Description: it is source code of 32 bit register and testbench for tht register written in verilog.
Platform: | Size: 13312 | Author: bhaskar | Hits:

[Compress-Decompress algrithms] COMPRESSION

Description: Simple LZW image compression implemented on Spartan-3e starter kit using Xilinx9.2 and Modelsim for testbench simulation.
Platform: | Size: 198656 | Author: amrabbas | Hits:

[VHDL-FPGA-Verilog] contador_n_bits

Description: n-bits counter vhdl with testbench. contador de nbits en vhdl con simulacion.
Platform: | Size: 1024 | Author: emiliano | Hits:

[Crack Hack] mini_aes_latest[1].tar

Description: AES 加解密 代码, 有文档说明，testbench-AES encoding decoding source code in HDL
Platform: | Size: 233472 | Author: wangbin | Hits:

[VHDL-FPGA-Verilog] rs_decoder_31_19_6_latest.tar

Description: RS解码器的FPGA实现，有TestBench-RS decoder FPGA to achieve, there TestBench
Platform: | Size: 13312 | Author: 王野 | Hits:

[Embeded-SCM Develop] FPGA-PCI

Description: 基于FPGA的PCI接口源代码及Testbench Verilog程序代码-fpag pci
Platform: | Size: 467968 | Author: lang | Hits:

[Graph program] GUI_Matting

Description: matlab编写的交互式image matting程序，包括：Poisson，Hillman，Ruzon等方法和源图像-matlab interactive image matting procedures, including: Poisson, Hillman, Ruzon methods and sources image
Platform: | Size: 2227200 | Author: andrew | Hits:

[VHDL-FPGA-Verilog] DDC

Description: 直接数字频率合成dds源码，cos三角函数生成代码，及测试代码，用于ddc前端测试的testbench。-direct digital frequency sysnthesis
Platform: | Size: 25600 | Author: wq | Hits:

[VHDL-FPGA-Verilog] BP062-BU-01000-r0p0-00rel0[1][1].tar

Description: AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
Platform: | Size: 313344 | Author: 李忠孝 | Hits:

[Other] alu

Description: ALU modeling verilog codes and testbench
Platform: | Size: 545792 | Author: neorome | Hits:

[VHDL-FPGA-Verilog] fir

Description: 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
Platform: | Size: 352256 | Author: hongwan | Hits:

[Communication-Mobile] scrambleanddescrambler

Description: 适合802.11a的scrambler与descrambler的设计，适合OFDM系统设计的初学者，有testbench可供参考-The scrambler and descrambler for 802.11a design, OFDM system design for beginners, there are available for reference testbench
Platform: | Size: 1024 | Author: jiaqi yuan | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 这个是我自己写的同步fifo ,供大家参考学习-this the syn-fifo,including testbench
Platform: | Size: 48128 | Author: 白桦 | Hits:

[VHDL-FPGA-Verilog] i2c-IPcore

Description: i2c的完整可用的Verilog代码，包含testbench.-i2c complete Verilog code is available, including the testbench.
Platform: | Size: 572416 | Author: 王宇 | Hits:

[VHDL-FPGA-Verilog] USB

Description: 用VHDL编写实现的USB接口控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the USB interface controller, bring their own testbench, after decompression project file can be opened with the ISE.
Platform: | Size: 156672 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] canbus

Description: 用verilog编写实现的CAN总线控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the verilog source code to achieve the CAN bus controller, bring their own testbench, after decompression project file can be opened with the ISE.
Platform: | Size: 1079296 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] Desktop

Description: 四选一多路选择器 modelsim testbench-Select more than one four-way selector modelsim testbench
Platform: | Size: 95232 | Author: 耿 | Hits:
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